To minimize the back-end-of-line (BEOL) interconnect portion of circuit delay, the conventional SiO2 dielectric (dielectric constant, k˜4.0) has been replaced with dense lower-k films (k<3.0). For further performance improvement, more parasitic capacitance reduction is required (k<2.5) for high-speed circuits.
Lowering parasitic capacitance can be achieved with new porous low k dielectrics, however most of the porous materials have relatively weak mechanical properties as compared to dense dielectrics. It is also difficult to integrate these materials with other BEOL module processes. For example, the conventional chemical-mechanical polish process has difficulty in polishing porous dielectric, and the conventional physical vapor deposition (PVD) diffusion barrier deposition technology cannot offer reasonable coverage on the surface of porous dielectrics.
Current art references directed to forming air dielectrics for microelectronic applications do not set forth techniques that can be employed in practical manufacturing processes. U.S. Pat. No. 6,057,224 discloses methods for making semiconductor devices having air dielectric interconnect structures. A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer, and non-sacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer; a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer. Additional similar interconnect structures can be stacked over a base interconnect structure.
U.S. Pat. No. 6,013,536 discloses an apparatus for automated pillar layout and method for implementing same. Disclosed is a method for automating support pillar design in air dielectric interconnect structures. The method includes selecting features having an interconnect dimension from a first mask. Providing an intermediate support pattern defining a pillar spacing. Identifying overlap regions where the features selected from the first mask overlap the intermediate support pattern. The method further including filtering the overlap regions to eliminate features that ale less than the interconnect dimension. The filtering being configured to define discrete pillar locations associated with the first mask.
The foregoing suggests removing a sacrificial material using pillars to form support on a semiconductor chip. The resulting structure is very unstable and cannot sustain any mechanical stress. For example, the structure cannot be further processed by employing a chemical-mechanical polishing process. It is not compatible with any existing packaging methodology. Randomly removing dielectric substances and replacing them with air cannot be implemented in the current manufacturing environment. Trapping of residual chemicals will cause yield and reliability failure, and the weak structure literally cannot protect the metallization levels of the chip.
U.S. Pat. No. 6,228,763 discloses a method of fabricating metal interconnect having inner air spacer. U.S. Pat. No. 6,329,279 discloses a method of fabricating metal interconnect having outer air spacer. US Patent Application Publication 2005/0037585 discloses a semiconductor device including air gap between semiconductor substrate and L-shaped spacer and method of fabricating the same.
A paper by L. G. Gosset et al., entitled “Integration of SiOC air gaps in copper interconnects,” Microelectronics Engineering 70 (2003), pp. 274-279, teaches another approach in which an extra lithography and extra etch step are utilized to generate an air gap. The added complexity increase costs and subjects the process to significantly increased process time per metal level.
Accordingly, it would be desirable to overcome the limitations of prior art approaches.